1. Field of the Invention
The present invention relates to photomask data processing technology for avoiding wafer pattern degradation due to insufficiency in the resolution of a stepper in semiconductor fabrication processes. In particular, the present invention relates to a mask pattern generating method and a mask pattern generating apparatus used in the generation of geometrical object patterns of photomask data.
2. Related Art of the Invention
In optical proximity correction (OPC) for processing photomask data so as to avoid pattern degradation on the wafer, it is indispensable to ensure the minimum line width and the minimum gap defined in photomask data.
In a prior art mask CAD processing technique, pattern line widths and pattern gaps are measured stepwise. Then, calculation is performed for each value of the dimension according to a correction table.
For example, in the case that the minimum pattern line width is ensured such that a pattern line width (L) 1 smaller than 140 nm is set into 140 nm as shown in FIG. 5, a line width correction (δ) 2 is set as follows.                When an edge line width greater than or equal to 130 nm and smaller than 132 nm is detected, the width is expanded by 10 nm.        When an edge line width greater than or equal to 132 nm and smaller than 134 nm is detected, the width is expanded by 8 nm.                    . . .                        When an edge line width greater than or equal to 138 nm and smaller than 140 nm is detected, the width is expanded by 2 nm.As such, line width correction is performed depending on the value of each pattern line width 1.        
On the other hand, in the case that the minimum pattern gap is ensured such that a pattern gap (S) 3 smaller than 180 nm is set into 180 nm as shown in FIG. 6, a line width correction (δ) 4 is set as follows.                When an edge pattern gap greater than or equal to 170 nm and smaller than 172 nm is detected, corresponding line widths are reduced by 5 nm each.        When an edge pattern gap greater than or equal to 172 nm and smaller than 174 nm is detected, corresponding line widths are reduced by 4 nm each.                    . . .                        When an edge pattern gap greater than or equal to 178 nm and smaller than 180 nm is detected, corresponding line widths are reduced by 1 nm each.As such, line width correction is performed depending on the value of each pattern gap 3.        
Such a prior art technique is disclosed in Japanese Laid-Open Patent Publication No. 2001-83689 entitled “Pattern correction method for semiconductor manufacturing mask, and recording medium recorded with the pattern correction method” (page 2 and Claims 1 and 2) and in Japanese Laid-Open Patent Publication No. H08-321450 entitled “Correction of mask pattern, formation of pattern, and photomask”.
Nevertheless, in such a prior art CAD processing technique where pattern line widths and pattern gaps are measured stepwise and then geometrical object logic calculation is performed for each value of dimension, the number of steps of correcting the pattern line widths is growing with increasing complexity in the OPC process caused by recent fine-structuring and integration-enhancement of semiconductor devices. This has increased the complexity in the mask CAD processing. As long as the prior art geometrical object logic calculation algorithm is used, the load to the mask CAD process will unavoidably continue to grow with the increase in the number of steps associated with the increase in the complexity in the OPC process.